Technical Note - Filter Test Using Pseudo Swept Frequencies
Frequency response is a key test item for filters. To measure the gain-frequency response, phase-frequency response, and group delay for filters, you can use the pseudo swept frequencies method. This method incrementally changes the input signal frequency to a filter (DUT), and measures the output signal from the filter.
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Mixed-signal Lecture Series: DSP-Based Testing Fundamentals 2 - Waveform Generation
ADC and DAC are the most typical mixed signal devices. In mixed signal testing, analog stimulus signal is generated by an arbitrary waveform generator (AWG) which employs a D/A converter inside, and analog signal is measured by a digitizer or a sampler which employs an A/D converter inside. The stimulus signal is created with mathematical method, and the measured signal is processed with mathematical method, extracting various parameters. It is based on digital signal processing (DSP) so that our test methodologies are often called DSP-based testing.
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Modulation Fundamentals 1 - Modulation and EVM Analysis
Modulation analysis is increasingly integral to the test strategies of integrated RF SOC transceivers. The trend is that as the industry gets closer to a single-chip cell phone, more and more mission mode tests need to be performed on the transceivers to make sure that all components of the radio are working together flawlessly. In RF SOC, nothing represents mission mode test better than error vector magnitude (EVM). An acceptable EVM measurement for a complex modulation format implies that a whole host of transmitter or receiver components are within specification. |
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Verigy Introduces...
In the last month, Verigy publicly introduced two important tools: Inovys Silicon Debug Solution for the V93000, and the V93000 HSM2200 for low-cost high-volume testing of high-speed memory. Read the details in the press releases to the right, and click through for more information! |
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Make Your VOICE Heard
Mark your calendars for VOICE 2008, the 3rd annual conference of V93000 SOC and V5000 Memory Series Users and Partners, September 23 and 24, 2008 in San Jose, Calif. |
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Verigy and Cadence Yield Learning Seminar Series
Join Verigy and Cadence for a seminar on using yield learning solutions that can help you achieve yield for your next nanometer design! Seminars will be held in Austin, San Jose and San Francisco. |
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June | 08
STATS ChipPAC Purchases Multiple Verigy Port Scale RF Solutions, Honors Verigy with a Top Supplier Award
NVIDIA Expands Capacity with Verigy V93000 SOC Tester Platform
Verigy Shortens SoC Manufacturers' Time to Yield with Inovys Silicon Debug Solution for the V93000 Platform
Verigy Appoints Bobby Cheng to Board of Directors, as Paul Chan Retires
UTAC Taiwan Acquires Verigy V93000 HSM2200 Systems for High-Volume Test of Next Generation DDR3 Memory Devices
SEMICON West 2008
Come experience the right ATE architecture at the Verigy booth. Tuesday-Thursday
July 15-17, 2008
Moscone Center
San Francisco, CA
Cadence and Verigy’s seminar on Optimized Solutions for Yield Learning
July 16, 2008
San Francisco, CA
VOICE 2008
The Annual Conference of
V93000 SOC and V5000
Series Users and Partners
Tuesday-Wednesday,
September 23-24, 2008
San Jose, CA
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