Low Phase Noise Reference Clock Signals & Verigy’s Port Scale Pure Clock
Applications requiring a very low phase noise reference clock signal to be applied to the DUT for certain measurements often challenge today’s ATEs. This paper outlines why low phase noise clocks are necessary, the pros and cons of possible solutions that exist on the V93000, and disadvantages of using on-board crystal for lowest phase noise clock generation. It then provides technical details and performance measurement results of the Port Scale Pure Clock along with detailed comparison to other approaches for reference clock generation. |
 |
Papers Invited for VOICE 2008
VOICE is the annual conference for the large and growing international community of Verigy V93000 SOC and Verigy V5000 Series users and partners. The conference will be Sept. 23-24, 2008, in San Jose, Calif. Paper proposals are welcomed; abstract deadline is May 1, 2008. |
 |
The Evolution and Future
of DfX in
Modern ICs
On January 7, 2008, Verigy announced acquisition of Invoys, a company providing innovative solutions for design debug, failure analysis and yield acceleration for complex semiconductor devices and processes. In this article, Al Crouch examines the value and efficiencies gained by embedding chips managing large digital content with test and measurement circuitry. |
 |
Verigy at SEMICON China
SEMICON China was held March 18-20, 2008 in the Shanghai New International Conference Center. This event report includes an overview of Verigy’s tradeshow floor presence, conference seminars, and lab demonstrations held at the Verigy Shanghai office. |
 |
|
 |
|
Read here for the latest Verigy technology innovations and 
