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Verigy Semiconductor Test Equipment Newsletter


features

With this issue, go/semi begins a new, monthly publishing schedule. Each month, we will feature a technical note, some fundamentals and “how to” articles, and a Q&A. The technology focus will rotate between consumer electronics (digital, mixed signal); high-speed and structural test, and wireless. Watch for more exciting changes over the next few months!

And always, your feedback is welcome. Email go/semi editor with your comments!

Application Note - Method for calculating SNR for Non-integer Cycle Sine Wave
Sine waves are the most fundamental waveform used in analog tests. In the mixed-signal IC testers which use DSP (digital signal processing), they are used to calculate test parameters such as THD (total harmonic distortion), SNR (signal-to-noise ratio) and frequency characteristics with FFT (fast Fourier transform). However, if the frequency of the measured sine wave is slightly different from expected frequency, and the number of cycles of the captured waveform ceases to be an integer, then FFT processing will cause leakage and the measurement accuracy will decline.

 
Mixed-signal Lecture Series: DSP-Based Testing Fundamentals 1
In DSP-based ATE, analog signals are generated by arbitrary waveform generators (AWG) which contain D/A converters (DAC) inside, and analog signals are analyzed by digitizers or samplers which contain A/D converters (ADC) inside. DAC and ADC are also typical devices under test for mixed signal ATE.
 
Question: "Why is my SNR result so bad?"
Question: The SNR result of an ADC or DAC is bad. I expected 60dB SNR of 1 MHz signal at 10 MHz bandwidth but it only has 45dB. What is wrong? (Junior Test Engineering of V Company)
 

Make Your VOICE Heard
Mark your calendars for VOICE ’08, the 3rd annual conference of V93000 SOC and V5000 Memory Series Users and Partners, September 23 and 24, 2008 in San Jose, Calif.

Verigy and Cadence Yield Learning Seminar Series
Join Verigy and Cadence for a seminar on using yield learning solutions that can help you achieve yield for your next nanometer design! Seminars will be held in Austin, San Jose and San Francisco.

 

May | 08

news

Verigy Announces Second Quarter Fiscal Year 2008 Earnings Release Date and Conference Call

Verigy Announces Shareholder Approval of Share Repurchase Program

ZMD Standardizes on Verigy V93000 SOC Series for Wafer Sort and Final Test of High-Performance Mission-Critical Devices

Papers Invited for VOICE 2008, Verigy's 3rd Annual Conference for Users and Partners

events

VOICE 2008
The Annual Conference of
V93000 SOC and V5000
Series Users and Partners
Tuesday-Wednesday,
September 23-24, 2008
San Jose, CA

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solutions
V93000 SOC V5000 Memory
V93000 HSM Applications
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