Your Program, Your VOICE

The technical program at VOICE 2008 begins in the trenches—with engineers and test specialists who use, configure, support and design Verigy test systems. Search for topics and discover how your colleagues are solving problems, improving productivity, and getting results.

This year's technical program will cover:

Test Techniques and Methodologies		Productivity Software and Tools
Communications and RF		DC and Mixed Signal
High-speed Digital Interfaces		Memory
Roundtables		Technology Kiosks

• Dynamic Supply Current Signature (Iddcs) Analysis Using the Qstar Module on V93000
  Richard Durant, LSI * Daniel Ahrens, LSI * Ariadne Salagianis, Verigy


• Yield Ramp Acceleration Using an Enhanced Diagnostic Solution
  Thomas Jackson, Cadence Design Systems * Anis Uzzaman, Cadence Design Systems
  Joe Swenton, Cadence Design Systems * Thomas Bartenstein, Cadence Design Systems


• Hiding Calculation Time with Multi-Threaded Test Program on V93000
  Martin Dresler, Verigy * Kyoichi Hatabu, Verigy


• Security Key Management and Programming on V93000 in a Production Environment
  Alberto Ascagni, STMicroelectronics * Luca Parma, STMicroelectronics * Simondavide Tritto, Verigy


• Efficient Scandump Technique
  Krishna Dusety, Qualcomm Inc * Neetu Agrawal, Qualcomm Inc


• ATE Test Method to Overcome Contact Resistance During HSTL Programmable Buffer Impedance Test
  Norman Pan, LSI * Dimitri Beausejour, Verigy


• A New Compatible V93000 Probe Card Design --- One Hardware for Wafer and Package Samples' Debug
  Harold Calderon, NXP Semiconductors * Melvin Cu, NXP Semiconductors
  Lhilbert Magpantay, NXP Semiconductors * Yun Dai, Verigy


• The "D2s-Framework": Targeting the TTM and TTV Challenges of Complex SOC DUT Registers Programming
  Neal Burgner, Qualcomm Inc * Gianluca Lombardi, Verigy * Daniel Blank, Verigy


• Characterization Techniques for a High Performance Digital Signal Processor SOC: Wavewizard to V93000 Testflow
  Roberta Myers-Baturin, Analog Devices * Heath Perry, Analog Devices * Mark Sleininger, Analog Devices


• A Technique to Automate Characterization of DUT Configurable Parameters Through the JTAG Port
  Babak Vaez, nVidia * Derek Lee, nVidia * Chris Koknat, Verigy


• Unified Volume Diagnostics for ATE and In-System Logic-Bist Using the Inovys Scan-Imager Solution
  Douglas Kay, Cisco * Lien Tran, Cisco


• Programmable Clock Controller for On-Chip, In-System Frequency Shmoo
  Han Ta, Cisco * Matthias Kamm, Cisco Systems


• Rapid Device Setup Through JTAG Protocol Language
  Chun Lai Brian Lin, Broadcom * Peter Obregozo, Verigy


• Fast and Secure OTP Production Solutions Using Certicom on the V93000
  Tom Heckman, Certicom * Fritz Mockler, STMicroelectronics * Frank Gurtovoy, Verigy


• Demystifying Digital Capture
  Amit Monga, Verigy *  Daniel Simoncelli, Verigy *  Michael Kozma, Verigy


• Highly Parallel DC measurements for Fab In-Line Monitoring
  Ernesto Shiling, IBM  * Lou Medina, IBM *  Bob Smith, Verigy


• Adaptive-Test at its Best with Verigy's V93000 and OptimalTest
  Gil Balog, OptimalTest

Productivity Software and Tools          Back to Top

• The V93000's New High Volume Manufacturing Capabilities
  Joel Taylor, Verigy * Henry Arnold, Verigy


• Robust Test Platform Conversion Using Galaxy Examinator
  Wes Smith, Galaxy * Kathleen Miller, Verigy


• Advanced Boundary Scan Diagnostic Tool on V93000
  Herve Brocheton, Verigy * Ming Lu, Verigy


• Automating Production and Engineering Testflow Re-Use Within the Manufacturing Environment
  William Polanco, Freescale Semiconductor * Erika Vasquez, Verigy


• Core-based Programming and Test IP Reuse in Mixed Signal SOC Test Development on V93000
  Zane Jiang, Verigy * ZuLiang Zhang, Verigy


• Protocol Aware Approach for ATE debug
  Sean Lu, Broadcom * Rodrigo Gonzalez, Verigy


• Efficient Test Program Development in a Multi-discipline Globally Distributed Team
  Ben Van der Waal, NXP Semiconductors * Hagen Goller, Verigy


• Test Assist - A New Way to Manage Verigy V93000 Test Programs
  Vikram Shirgur, Nano ISI * Vinuta Shetty, Nano ISI * Sangeet Karamchandani, Verigy


• Integrating ATE Test in the Design Flow - A Case Study
  Somnath Sen, Cypress Semiconductor * Kirit Kichadia, Simutest * Sreenivas Gandavarapu, Cypress Semiconductor


• Getting More out of SmarTest Eclipse Work Center
  Michael Vogt, Verigy * Michael Kozma, Verigy * Chris Buoy, Verigy


• A Novel Way to Explore V93000 Test Programs with Web Browser
  Zuliang Zhang, Verigy * Zhijun Xue, Verigy

Communications and RF          Back to Top

• A Fast and Accurate Method to Perform Evaluation Board to Production Board Correlation by Using Non-linear Device Characteristics
  Michael Engelhardt, Verigy


• Concurrent Test Implementation on a 2G/3G Baseband Device
  Fabien Perez, NXP Semiconductors * Markus Vogt, Verigy


• Multi-Threading on V93000 Reduces Multi-Site RF Test Time on Intel Front-End Transceiver
  Leon Sassoon, Intel * Michael Engelhardt, Verigy * Jason Smith, Verigy * Joe Kelly, Verigy


• Making MIMO Measurements in a Manufacturing Environment
  Vivek Verma, Verigy * Craig Kanetake, Verigy


• A High-Parallelism Low-Cost Solution for RF-Digital Receiver Test on V93000
  Jie Ren, Verigy * Liang Ge, Verigy


• Concurrent Test Techniques to Reduce MCU+RF Single Chip Test Time
  Jean Mounie, Freescale Semiconductors * Eric Aubry, Verigy


• IQ Phase and Magnitude Mismatch Calibration
  Jonathan Rimon, Verigy


• Demodulating WIMAX - An Introduction to New V93000 Demodulation Capabilities
  Edwin Lowery, Verigy * Guenther Bleifuss, Verigy * Hiroshi Kikuyama, Verigy


• On the Use of Multi-Tone for the Measurement of Inter-Modulation Distortion in RFIC
  Cheng Huang, Verigy


• Pure Clock Solution for Improved PLL Performance
  Roger McAleenan, Verigy * Oscar Solano, Verigy * Khaled Ben-fatma, Verigy


• Testing Bluetooth 2.0 + EDR with Port Scale RF: Challenges and Solutions
  Martin Dresler, Verigy * Paul Chen, Verigy * Joe Kelly, Verigy


• Wideband RF Measurement
  Frank Goh, Verigy


• RT-SPU to Manage Small Signal Test Requirements for Effective Test Time
  Ilya Tsiperfal, Broadcom * Siva Raman, Verigy

DC and Mixed Signal          Back to Top

• Reducing the COT with V93000 Per Pin Time Interval Analyzer
  Don Blair, Verigy


• A DFT for Measuring Rdson and Its Application on V93000 SOC
  Maarten Derks, NXP Semiconductor * Jiamin Wang, Verigy


• Utilizing DSP Filters of Local DSP and RT-SPU in DAC Linearity Test for Higher Throughput and Accuracy
  Satoshi Nomura, Verigy


• Revolutionary Dynamic DC Measurement Using DC Scale
  Aether Lee, Verigy * Takashi Shibata, Verigy


• Implementation of Video Singal Test for a TV-IC Device
  Teruaki Itabisashi, Renesas Technologies * Yasuhiro Kizu, Verigy


• Optimized Solutions to Measure PMIC
  Sophia Zhang, Verigy


• Sample Rate Conversion. The Possibility to Create as Many Clock Domains as Available Digitizers
  Achim Rosenau, NXP Semiconductors * Erhard Schuetz, Verigy

High-speed Digital Interfaces          Back to Top

• 4:1 HDMI Switch: 5 ms for Testing: Myth or Reality?
  Stephen Rimbault, NXP Semiconductors


• Novel Clock Signal Analyses with a Waveform Sampler - Rise/Fall Time, Jitter and Jitter Separation
  Hideo Okawara, Verigy


• A Time Domain Reflectometry Kit for ATE Test Fixtures
  Ross Winters, Intel * Jose Moreira, Verigy * Heidi Barnes, Verigy * Callum McCowan, Verigy


• Solving MIPI D-PHY Test Challenges with V93000 SOC Test System, Part 2 (DUT transmitter tests): Techniques to Properly Detect Multi-level Signals with Different Termination Requirements
  Ricky Lau, AMD * Yu Hu, Verigy * Stefan Walther, Verigy * Danile Simoncelli, Verigy


• PCI Express Protocol Testing on Verigy V93000 SOC Pin Scale 3600
  Toby McPheeters, Broadcom * Jim Chua, Broadcom * Jinlei Liu, Verigy


• Functional Testing of PCI-Express using Pin Scale 3600
  Steve Karako, Freescale Semiconductors * Michael Kozma, Verigy * Barry Schmidt, Verigy

Memory          Back to Top

• GDDR5 Test Challenges and Their Solutions on the Verigy 93000 HSM Series
  Han-Ho Jin, Hynix Semiconductor Inc. * Hee-Won Kang, Hynix Semiconductor, Inc.
  Hubert Werkmann, Verigy * Ji-Won Seo, Verigy


• Utilize V5XXX Features to Test Beyond 100MHZ
  Houfeng Zuo, Verigy


• V5000 Code Structure Standardization and Automatic Generation
  Jian Zhang, Verigy * Brian Lu, Verigy


• DDR3 On-Die Termination Test
  Chao Wu, Verigy


• Flash Memory Bitmapping - Future Challenges and Solutions
  Mark Greenwood, Verigy


• Mass Production Test Solution for XDR 4.8Gbps on the Leading Edge of DRAM
  Kunihiko Kato, Elpida * Takeshi Sonoda, Verigy


• Factory Automation in a 300mm Memory Test Environment
  Larry Goldsmith, Verigy


• A Comparison of Pin Electronics Designs to Increase Test Parallelism for Memory Devices
  Scott West, Verigy


• Closing the Loop Between Design and Test: Enabling the Validation and Debug of MTL-based Memory Test Patterns by Logic Simulation
  Alexander Roskin, Verigy * Daniel Blank, Verigy


• Sub-40nm Multi-Level Flash Challenges for Production Test
  Paul Okino, Verigy

Round Tables          Back to Top

• Yield Learning
  Erik Volkerink, Verigy


• DUT Board Design Process
  Fredrick Crist, Verigy *  Kelley Demange, Verigy


• Utilizing V93000 CCT to Minimize Vector Memory Requirements
  Meir Gellis, Test Insight *  Dimitry Angert, Test Insight


• The Concept of Differential Signalling on Pin Scale 400
  Stefan Walther, Verigy * Michael Kozma, Verigy


• A Comprehensive Design for Test Approach
  Martin Froehle, AMD * Markus Seuring, Verigy


• STDF Fail Datalog Standard: Overview and Examples
  Ajay Khoche, Verigy


• Why Statistical Analysis is Critical for Correlation and how it is Managed on V93000?
  Phanu Kisamanon, Broadcom * Siva Raman, Verigy


• Characterizing "at the DUT" on the V93000: Focus Calibration and Loadboard Characterization
  Jose Moreira, Verigy *  Heidi Barnes, Verigy


• Quick Hardware Prototyping
  David Johansen, Verigy


• Sharing Pinscale V93000 Licensing Globally
  Jason Wiseman, Freescale Semiconductor * Tom Micek, Freescale Semiconductor
  John Pitts, Freescale Semiconductor * Erika Vasquez, Verigy


• Online Adaptive Test Techniques for the Verigy V93000
  Taylor Scanlon, Pintail Technologies


• New STDF Validation Tool for Scan Datalog
  Phil Burlison, Verigy

Technology Kiosks          Back to Top

• Selected TOP Enhancements of SmarTest 6.3 - 6.5
  Rainer Held, Verigy


• V93000 Technical Documentation Center
  Falk Kronsbein, Verigy


• New SmarTest Tabular Test Numbering Solution
  Ryan Lucy, Verigy * Gerd Bleher, Verigy


• IP Reuse (Pin Alias Support and Merge Collision Resolution) on the Verigy V93000
  Rainer Held, Verigy * Rong Xu, Verigy


• Using the INOVYS Silicon Debug Solution on the V93000 to Quickly Identify Yield Limiting Issues in Nanometer Designs
  Michael Braun, Verigy


• VI Curve Tracer
  Aether Lee, Verigy * Keita Gunji, Verigy


• SmarTest Usability - Future Vision
  Yoshiki Toyama, Verigy


• Test Method API for Analog and RF Instrument Setups
  Stefan Gross, Verigy * Frank Dollendorf, Verigy * Johannes Hauf, Verigy


• Productivity Improvements of the Port Scale RF Online Debugging
  Hao Zhang, Verigy


• Verigy Tools Session
  Holger Kist, Verigy