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Tracks
TTM - Time to Market
SWPT - Software and Productivity Tools
HWLB - Hardware and Loadboards
HSM - High Speed Memory
Memory
RF
TdT - Touchdown Technologies

	Room: Sunset 1	Room: Sunset 2	Room: Carlsbad A/B	Room: Cardiff	Room: Solana	Room: Del Mar
	Tracks SWPT	Tracks SWPT TTM	Tracks TTM HWLB	Tracks SWPT TTM RF HWLB	Tracks HWLB TTM	Tracks MEMORY HSM TdT
Day One - April 13, 2010
11:00 AM 45 Mins	84: Reducing Cost of Test using SmarTest Execution Profiles	81: SOC Device Setup: Advancing from Physical to Logical Level	103: Design, Verification, and Real Life Use of the V93000 Direct Probe Solution	77: PortScale FE24 & FE12 Performance Comparisons	19: IO Interface Characteri- zation - an Application of DNA Tools	106, Future Memory Technologies and Test Challenges
Lunch - 60 Mins
1:00 PM 30 Mins	24: Improving Throughput of a Wireless Combo Device using SmartCalc	48: Use SmarTest to implement core based design and IP reuse	104: ATE Loadboards and the Art of Engineering the Signal Path Capacitance for Power, Current, and Slew Rate	12: Characterizing the Open Loop VCO Frequency of an RF Transceiver Using PSRF	112: Genera- ting Phase Shift to Adequately Test Self-Jammer Circuits	29: V6000 TTR by Ping Pong and ECC function
1:45 PM 30 Mins	39: V93000 SmarTest Mixed Signal Integration	98: New SmarTest Features for IP Reuse	73: A Fast Approach to Localize Scan Test Failure on V93000	50: Efficient and Full Parallelism in Octal-site FM RX Tests on V93000	94: Using a More Sensitve Continuity Test to Achieve a Robust and Consistent Connection Between a Part and Socket	16: An Unprecedented Solution on DDR3
2:30 PM 30 Mns	44: Eclipse Work Center Centric use Model - Power of Integration	67: Speeding Test Program Development with a Code Re-use Library	20: Enhanced Vector Memory Compress Methodology Using V93000 per-pin capability	88: Test Throughput Improvement for Multi-Site Testing of an RF Silicon Tuner Device	85: Next Generation Nano-Technology DC Test Methods	60: Overview of HSM6800 Features and their Usage to Test High-speed Memories
Break - 30 Mins
3:45 PM 45 Mins	65:Efficient and Rapid Creation of V93000 Test Programs from STILVCD and WGL	66: Developing an Advanced Production Interface for V93000	11: Using V93000 Test Time Reduction techniques to Test 8 PMICs in 6 seconds	97: Optimizing Testing of 65nm QAM RF Tuners	49: Evaluate 10Gbps CDR Performance with V93000 PinScale HX	113: Characterizing Jitter on GDDR5 Devices
4:45 PM 30 Mins	96: Interfacing Design Tools to the V93000	114: API Based Analog Control file Usage for Quick Development Work and Easy Debug and Optimization Capabilities in Smartest 6.5.X.	8: Marvell Multimedia Processor DDR Source-Sync Setup and Hold-Time test on the V93000	30: Approaches to Handle Incoherent Measurement	87: Application of the ppTIA for Jitter Trend and Spread Spectrum Clock Measure- ments	7: Equalization in the HSM6800 Pin Electronics
Day Two - April 14, 2010
1:00 PM 45 Mins	92: Universal Test Methods: Getting the Most out of the New V93000 Test Method Development Environment	63: Using On-tester Scan Chain Diagnosis in Real-time for Faster Yield Learning	46: Concurrent Test on the V93000	115: Using PhotoMOS Devices as a Replacement of Mechanical Relays for Loadboard Design	74: Calibration of the Driver Eye Height for Receiver Tolerance Measure- ments	107: A Low-force MEMS Probe Solution for Single-touch Full-wafer DDR3 Memory Test
2:00 PM 30 Mins	21: Design and Implementation of an Object-oriented Test Method Library for V93000	2: Testing of High Speed High Resolution DACs with Ensemble Averaging	61: A Concurrent Test Solution on PSRF for Bluetooth Device	101: Construction of Wafermaps for Analysis of Verigy Final Test Data from Singulated Die	64: Beating Verigy-V93000 Timing Specification with Focus Calibration	108: Final Test Cost Savings in Memory Test
2:45 PM 30 Mins	18: Digital Sequenced Control of Iinstruments made Easy with Hyper Instrument API	6: Optimize Sampling Rate for HSIO PRBS Waveform Analysis with 6G Sampler	100: Concurrent Test: Implement- ation and Recomm- endations	79: ATE Loadboard Layout and Interfacing for High RF Pin Count Devices	69: An Efficient HSIO Eye Measurement Technique using Under-sampling on PS3600	109: RA Test Time Challenges
Break - 15 Mins
3:45 PM 30 Mns	75: Schematic Viewer Tool	70: Optimized Embedded DRAM Test Solutions for Parallel Efficiency	4: High-Speed ADC Testing with Multiple Clock Domains	41: An Adaptive Compensation Method for Wideband RF on V93000	42: Advance RF Wafer Sort Testing in Production	51: Daisy Chain Driver Sharing on V6000 APIM
4:00 PM 30 Mins	34: Embedded Interpreter for Testmethods	99: Applying DPS32 as a Cost-Effective Analog Module: 16-Site Test for an Electronic Compass Device	36: High-speed ADC Testing: Required Clock and Signal Integrity	15: Measure UWB on the V93000: Undersampling with the Wide Band Sampler	102: DigRF v4 on the V93000 PS3600	111: Benefits of an Energy Efficient ATE Architecture for Memory Test

 

All new for 2010, VOICE now offers:

• Workshops  Three separate tutorials.
• Featured Papers  Sessions with 45-minute, full conference-style papers with presentations.
• Expert Discussions  Two-hour R&D meetings and roundtable discussions.
• A Fully Revamped Program Structure  Sessions give you the specifics of a topic and allow time to interact with the author:
  • Short-form Presentation  Thirty-minute long presentations with extensive speaker notes and additional supporting materials (optional) and indicate the category you're targeting.
  • Long-form Presentation  Forty-five minute long presentations with extensive speaker notes, additional supporting materials such as V93000 devices, scripts, etc., and indicate the category you're targeting.