 |
|
|||||||
 |
|
|||||||
|
Verigy’s culture of innovation generates technology-leading products that help our customers to achieve fastest time-to-market and cost-competitiveness. |
We offer a single platform for each of the two general categories of devices being tested: 
"Tester-per-pin" architecture Our V93000 Series platform is made more scalable by its “tester-per-pin” architecture. SOCs, SIPs and high-speed memory devices are complex and sophisticated, and each device pin may need to be tested independently for a thorough and complete test. Different SOCs, SIPs and high-speed memory devices have different numbers of pins. By being able to select – and easily change – the number of digital cards and pins in the system, the exact test system requirements can be specified even in a changing environment. A single V93000 Series system can test both different types and different numbers of devices by loading different test programs onto the test processor. This ability to quickly change the type and number of devices being tested makes our test systems particularly well suited for subcons who test a wide range of products. "Tester-per-site" architecture Our V5000 platform is made more scalable by its ‘‘tester-per-site’’ architecture. Designed specifically for memory testing, this architecture enables highly parallel and efficient testing of memory devices as well as a high level of scalability by utilizing a separate and independent test processor for each test site of the system. The test processor contains a dedicated set of resources, including power supplies, test pattern generators, test sequence controllers and error detection circuitry, that can be independently applied to each device under test. This independent control of each device under test ensures the flexibility of testing a wide variety of different memory types without a change in tester hardware. ASIC-based test processor Both platforms benefit from greater scalability, flexibility, performance and accuracy through the use of an ASIC-based test processor for testing devices at each test site of the system. The test processors achieve high performance and test a large number of devices in parallel while being capable of fitting into a test system that occupies a relatively small footprint. The use of a separate and independent test processor at each site of the system means that the speed of the test will stay the same as sites are added for additional parallel testing. Liquid cooling The V93000 SOC contains a very large number of high performance ASICs concentrated into a small amount of space, which requires dissipating a considerable amount of heat. Liquid cooling provides lower operating temperatures, greater system reliability, reduced operating costs, improved accuracy and speed and quieter and cooler operation than the traditional air-cooling used in many of our competitors’ products. Programmable Interface Matrix Our optional Programmable Interface Matrix helps to further boost the parallelism of our V5500 system for high volume production testing of packaged devices. Much like a telephone switching system routes callers to their destinations, the Programmable Interface Matrix routes testing resources to the individual memory or MCP that requires testing. The switching is purely electronic, resulting in a faster and more reliable resource switching than mechanical relays, with less downtime. It enables testing of up to 512 devices in parallel for complex and high-pin-count MCPs and the flash memory prevalent in mobile devices. The Programmable Interface Matrix’s 24,576 pins ensure that even highly complex memory devices can be tested with high parallelism and thus at lower cost. |
Test Technology Library Learn from Verigy experts about the latest industry trends, challenges, methodologies, and our products. Register and gain access to over 50 technical papers, and be notified by email as new papers are added. Visit the Test Technology Library and register today. |
Related Links |