Yield ramp is one of the biggest challenges in nanometer designs. Difficulty arises as it is not possible to accurately predict yield before actual silicon and forcing many products to not reach required yield within their market window. Product based yield learning with data from actual silicon is essential for ramping a product. It is also imperative that the learning process is optimized for throughput and accuracy to avoid market opportunity and profit losses as well as costly re-spins. Verigy, together with Cadence ®, are leading the revolution in semiconductor design and test convergence, providing customers with innovative test solutions for design debug, production yield ramp, and failure analysis.

The joint seminar between Verigy and Cadence highlights the integrated architecture for yield learning by optimizing the cost of information, improving throughput, and accuracy of diagnosis and providing methods to address yield problems earlier to improve yield economics.