Speed Clustering of Integrated Circuits
Published 28-Oct-2004, by Kenneth A. Brand, et al. at the Test Conference, 2004, Proceedings, International, October 26-28, 2004, Pages: 1128 - 1137.

Parallel Test Reduces Cost of Test More Effectively than Just a Cheap Tester
Published 16-Jul-2004, by Jochen Rivoir, at the Electronics Manufacturing Technology Symposium, 2004, IEEE/CPMT/SEMI 29th International, Vol., Iss., July 14-16, 2004, Pages: 263 - 272.

Lowering Cost of Test: Parallel Test or Low-Cost ATE?
Published 19-Nov-2003, by Jochen Rivoir at the Test Symposium, 2003. ATS 2003. 12th Asian, Vol., Iss., 16-19 Nov. 2003, Pages: 360 - 363.

Leveraging P1450.6 for Faster Production Test Development
Published 28-May-2003, by Domenico Chindamo, et al., at the European Manufacturing Test Conference, Maastricht, The Netherlands, 25 - 28 May 2003.

Efficient Seed Utilization for Reseeding Based Compression
Published 01-May-2003, by Erik H. Volkerink, et al., at the VLSI Test Symposium, 2003, Proceedings, 21st, 27 April-1 May 2003, Pages: 232 - 237.

Test Economics for Multi-Site Test with Modern Cost Reduction Techniques
Published 02-May-2002, by Erik H. Volkerink, et al., at the VLSI Test Symposium, 2002 (VTS 2002), Proceedings 20th IEEE, Vol., Iss., 2002, Pages: 411 - 416.

An Evolution to a DFT-Centric Test Paradigm that Scales with Technology Progress
Published 01-Jun-2001, by Wilhelm Radermacher and Jochen Rivoir, at the European Test Workshop, May 29 - June 1, 2001, Stockholm, Sweden.

Tackling Test Trade-Offs from Design, Manufacturing to Market Using Economic Modeling
Published 2001, by Erik Volkerink, et al., at the Test Conference 2001, Proceedings, International, Vol., Iss., 2001, Pages: 1098 - 1107.