Analyzing and Addressing the Impact of Test Fixture Relays for Multi-Gigabit ATE I/O Characterization Applications
Published by Jose Moreira, Heidi Barnes, Guenter Hoersch; 1-4244-1128-9/07/ ©2007 IEEE

Passive Equalization of DUT Loadboards for High-Speed Digital Application
Published December 2007, Jose Moreira, Verigy; Michael Howieson, Mark Broman, Thin Film Technologies, at Voice 2007

Efficient Data Collection for Volume Diagnosis on V93000
Published 26-October-2007, by Michael Braun, et al. at the 1st IEEE International Workshop on Automated Test Equipment: Vision ATE 2020 - 10/26/2007.

Influence of Dielectric Materials on ATE Test Fixtures for High-Speed Digital Applications
Published 28-July-2007, by Jose Moreira, et al. at the Sixth International Kharkov Symposium on Physics and Engineering of Microwave, Millimeter and Submillimeter Waves (MSMW’07).

Addressing the Broadband Crosstalk Challenges of Pogo Pin Type Interfaces for High-Density High-Speed Digital Applications
Published 7-June-2007, by Bela B. Szendrenyi, et al. at the IEEE MTT-S 2007 International Microwave Symposium, 7 June 2007.

Differential PCB Structures using Measured TRL Calibration and Simulated Structure De-Embedding
Published 31-January-2007, by Heidi Barnes, et al., at DesignCon 2007 on 31 January 2007.

Development of a Pogo Pin Assembly and Via Design for Multi-Gigabit Interfaces on Automated Test Equipment
Published 13-December-2006, by Heidi Barnes, et al. at the Asia-Pacific Microwave Conference 2006, 13 December 2006.

Passive Equalization of Test Fixtures for High-Speed Digital Measurements with Automated Test Equipment
Published 20-Nov-2006, by Jose Moreira, et al. at the 2006 International Design and Test Workshop, November 19-20, 2006.

Parametric Testing of a 10Gbs I/O Cell in Production through a Parametric Loopback Approach with Retiming
Published 20-Nov-2006, by Jose Moreira, et al. at the 2006 International Design and Test Workshop, November 19-20, 2006.

Comparison of Measurement Method by Analog and Digital Resource for High Speed Serial Interface
Published 09-Dec-2005, by Takashi Ito at the Semi Technology Symposium in Semicon Japan 2005, Proceedings, 7-9 December 2005.

A Test Case for 3Gbps Serial Attached SCSI (SAS)
Published 10-Nov-2005, by J. Liu, et al. at the Test Conference, 2005, Proceedings, International, 8-10 Nov. 2005.

Addressing the Challenges of Implementing an At-Speed Production Test-Cell for 10Gb/s Wafer Probing
Published 2-Feb-2005, by Jose Moreira, et al. at DesignCon 2005, 31-Jan - 2-Feb, 2005.

A Model-Based Test Approach for Testing High Speed PLLs & Phase Regulation Circuitry in SOC Devices
Published 28-Oct-2004, by Bernd Laquai at the Test Conference, 2004, Proceedings, International, 26-28 Oct. 2004, Pages: 764- 772.

Integrating Boundary Scan into Multi-GHz I/O Circuitry
Published 28-Oct-2004, by Jeff Rearick, et al. at the Test Conference, 2004, Proceedings, International, 26-28 Oct. 2004, Pages: 560 - 566.

Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATE
Published 28-Oct-2004, by Guido Schulze, et al. at the Test Conference, 2004, Proceedings, International 2004, Pages: 1303 - 1312.

Divide and Conquer Based Fast Shmoo Algorithms
Published 28-Oct-2004, by P. Patten at the Test Conference, 2004, Proceedings, International, 26-28 Oct. 2004, Pages: 197 - 202.

Testing High Speed Serial IO Interfaces Based on Spectral Jitter Decomposition
Published 14-Oct-2004, by Rainer Plitschka and Bernd Laquai at DesignCon 2004, 11-14 October 2004.

Enabling the PCI Express(TM) Ramp -- ATE Based Testing of PCI Express Architecture
Published 01-Aug-2004, by Hubert Werkmann at Euro DesignCon 2004, 11-14 October 2004.

Sequential Bayesian Bit Error Rate Measurement
Published 01-Aug-2004, by Lee Barford at the Instrumentation and Measurement Technology Conference, IEEE Transactions on Volume 53, Issue 4, Aug. 2004, Pages: 947 - 954.

Serial ATA Testing with Analog Tester Resources
Published 16-Jul-2004, by Hideo Okawara at the Electronics Manufacturing Technology Symposium, 2004, IEEE/CPMT/SEMI 29th International, July 14-16, 2004, Pages: 212- 217.

Delay Defect Screening Using Process Monitor Structures
Published 29-Apr-2004, by Erik Volkerink at the VLSI Test Symposium, 2004, Proceedings, 22nd IEEE, 25-29 April 2004, Pages: 43 - 48.

Managing the Multi-Gbit/s Test Challenges
Published 02-Oct-2003 by Ulrich Schoettmer and Bernd Laquai at the Test Conference, 2003, Proceedings, ITC 2003, International, Volume 1, Sept. 30-Oct. 2, 2003, Page(s): 1310 - 1310.

First IC Validation of IEEE Std. 1149.6
Published 02-Oct-2003 by Suzette Vandivier, et al. at the Test Conference, 2003, Proceedings, ITC 2003, International Volume 2, Sept. 30-Oct. 2, 2003, Pages: 79 - 86.

Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture
Published 01-May-2003, by Jeff Rearick at the VLSI Test Symposium, 2003, Proceedings, 21st, 27 April-1 May 2003, Pages: 15 - 21.