Platform
DUT Loadboard Layout for Multi-Gigabit Bi-Directional Interfaces
Published December 2007, Jose Moreira, Heidi Barnes, Hubert Werkmann, Verigy, at Voice 2007
Optimizing the Whole Test System to Achieve Optimal Yields and Lowest Test Costs
Published 16-Jul-2004, by Dave Haupt at the Electronics Manufacturing Technology Symposium, 2004, IEEE/CPMT/SEMI 29th International, July 14-16, 2004, Pages: 282 - 294.
Future ATE for System on a Chip... Some Perspectives
Published 02-Oct-2003, by Tom Newsom at the Test Conference, 2003, Proceedings, ITC 2003, International, Vol.1, Iss., Sept. 30-Oct. 2, 2003, Page(s): 1301- 1301.