Outdated Link

The Verigy web site has been reorganized. Please update the bookmark or link that you followed to get here. In a few seconds you will be redirected to our new public products page.

Verigy Home> V5000 Memory> V5500

V5500

Summary

Highest utilization for single insertion MCP test and breakthrough parallelism for discrete Flash final test, resulting in lowest cost of test

The Verigy V5500 addresses the test challenges of complex multi-chip packaged devices (MCPs) and the need for the highest possible throughput for low and high pin count discrete Flash. The tester-per-site architecture of the V5500, combined with the Verigy Programmable Interface Matrix technology, optimizes single insertion testing of MCPs with multiple memory types (including Flash, DRAM and SRAM) resulting in industry leading tester utilization and throughput. The Matrix also enables up to 4x parallelism at final test for discrete NAND and NOR devices: up to 320 devices in parallel.

The Verigy V5500 offers the first true high utilization, single-insertion final test solution that dramatically reduces the cost of MCP test. The V5500 is a complete final test solution that addresses the complex test challenges faced by manufacturers of MCP and discrete Flash memory devices. The V5500 leverages Verigy's industry-leading memory test expertise into final test, continuing the tradition of breakthrough cost-of-test solutions.

Taking advantage of Verigy's single-insertion MCP test and high parallelism discrete Flashtest solutions, manufacturers of single- and multi-memory devices reap considerable savings relative to capital investment, consumable expenses, test time reduction, floor space and reliability, over traditional multi-insertion or other high pin count testing alternatives.

The Verigy Programmable Interface Matrix technology, combined with the V5500's Tester-Per-Site architecture, enables optimized single insertion testing of MCPs containing multiple memory types including Flash, DRAM and SRAM. This technology breakthrough produces significantly higher tester utilization and throughput than ever before.

The V5500 also provides unmatched parallelism for testing discrete NAND and NOR Flash devices at final test. When set to High Parallelism mode, the Matrix enables testing of x320 NAND and x256 NOR devices to fully utilize today's leading edge x320 handlers.

The V5500 is designed to meet today's and tomorrow's MCP and high-parallelism final test challenges head-on.

First ever cost-effective final test solution for MCPs

High parallelism yields unmatched throughput for discrete memory final test

View the V5500 Matrix Demo

Related Links

Article Reprints

Brochures & Product Overviews

Data Sheets

Product Images

Promotional Materials

Available Actions

Subscribe to RSS

Printer Friendly Page

Highlights

V5500 with Matrix Wins "Test & Measurement World" Honorable Mention Award

V5500 Matrix Flash Demonstration

Agilent Enters Final-Test Market, Introduces Tester for MCPs, Discrete Flash Memory
PALO ALTO, Calif., July 12, 2005 -- Agilent introduced the Versatest Series Model V5500, the first cost-effective final test solution for multichip package devices (MCP) and discrete flash memory.