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V93000 HSM
Features & Benefits
Key Specifications & Requirements
Industry Challenges
Support
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Summary

Fastest memory ATE solution offers at-speed IO and at-speed core test for new class of high-speed DRAMs

The Verigy V93000 HSM Series – the fastest DRAM tester available – is targeted at final test of high-speed memories offering 3.6Gbps at-speed IO and at-speed memory core test to ensure the required test quality and fast yield learning at competitive cost-of-test. Verigy V93000 High-speed Memory (HSM

It offers dedicated features for XDR and GDDR but also the flexibility to address all future DRAM technologies ensuring investment protection.

  • Ensured quality and fast yield learning
  • Manufacturing Flexibility and Investment Protection
Low technical risk, Proven Architecture for Speed & Accuracy

The V93000 HSM Series re-uses the proven per-pin timing architecture of the V93000 platform for high-speed test and leverages technology components for low investment reasons. However The HSM Series is featuring significant architectural extensions addressing the requirements for final test of DRAMs, thus becoming a TRUE memory-ATE-per-pin. Per-pin memory ATE architecture will be needed for future emerging DRAM technologies.

Highest Manufacturing Yields

Besides the per-pin timing architecture, which provides lowest jitter, the HSM Series features source synchronous and parallel eye-finding functionality to support new IO concepts for GDDR and XDR respectively. These functions enlarge the timing margins and thus yield.

Lowest Test Time

The fastest data rate of 3.6Gbps not only provides unmatched test quality, but it provides a cost advantage versus competitive solutions deploying a “double clocking” methodology which adds a 50% cost penalty.

Cost competitive, high parallelism solution for targeted speed class

This high volume manufacturing solution comes with an engineered test-cell, which ensures reliable operation, high uptime and seamless support. The HSM Series supports a parallelism of 16x sites (for 16x organized XDR, 32x organized GDDR DRAMs) in a single test-head. Single test-head solutions offer an inherent ~15% higher effectiveness. This, paired with parallel eye-finding/data training, makes the HSM Series the most cost-effective production test solution for high-speed memories at ensured device quality.

The HSM Series is available in two speed classes. A reduced speed version with 2.2Gbps data rate (speed binned HW) and a top-speed version with 3.6Gbps.


Key Capabilities

The Verigy V93000 HSM Series has the following key capabilities:
  • At-speed IO test up to 3.6Gbps
  • At-speed memory core test up to 3.6Gbps (>3.6Gbps with “double clocking”)
  • At-speed failure capture up to 3.6Gbps, incl. Bitfailmap (BFM) Viewer
  • Differential and low signaling support
  • C++ test pattern programming via MTL
  • CWOF timing architecture, lowest jitter
  • Parallel Eye-Finding, Source Synchronous
  • 16x site parallelism in single test-head
  • Engineered Test-Cell


 



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Verigy V93000 HSM High-Speed DRAM Tester Receives Honorable Mention in Test & Measurement World 2007  CUPERTINO, Calif. - Jan. 11, 2007 - Verigy (NASDAQ: VRGY), a premier semiconductor test company, today announced that the Verigy V93000 High-Speed Memory (HSM) Series DRAM tester was recognized in the honorable mentions category. The V93000 HSM Series was one of 24 products selected by Test & Measurement World's editors for honorable mention as part of its annual Best in Test awards.