See Verigy at ITC 2008
October 28-30, 2008
Visionary and Enduring
Stop by and take a look at the most complete fault localization tool in the industry in booth #93 at the 2008 International Test Conference in Santa Clara, CA. Our technical experts will be on hand delivering private presentations and demonstrations of the newly introduced Inovys Silicon Debug Solution.
Learn more about ITC 2008
Faster, More Efficient Debug
The Inovys Silicon Debug Solution combines the revolutionary FaultInsyte software with the V93000 SOC test system to deliver an integrated solution that enables rapid detection and diagnosis of electrical failures on complex SOC devices.
Visit us in booth #93 to learn more about this innovative solution or click here to schedule your live demonstration today!
Where
Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054
Dates and Times
Tuesday, October 28, 10:30am-5:45pm
Wednesday, October 29, 9:30am-5:45pm
Thursday, October 30, 9:30am-2pm
Who Should Attend
Test and product engineers and managers
Registration
To register for admission to the Exhibit Hall, click here.
What to Expect
Learn how innovative Verigy test solutions deliver bold new functionality and ever-increasing performance while lowering cost of test.
You will have multiple opportunities to see the Verigy as we present papers, teach tutorials and participate in panel presentations.
- Lecture: Beyond 10 Gbps? Challenges of Characterizing Future I/O Interfaces with ATE – Wednesday, October 29, 8:30-10:00AM
- Presentation: Find it. Fix it – with the Inovys Silicon Debug Solution – Wednesday, October 29, 8:30-10:00AM
- Panel: Will Test Compression Run Out of Gas? – Wednesday, October 29, 4:00-5:30PM
- Panel: Yield Learning – Who Gains, Who Picks Up the Tab? – Wednesday, October 29, 4:00-5:30PM
- Paper: A Method to Generate a Very Low-Distortion, High-Frequency Sine Waveform Using an AWG – Thursday, October 30, 8:30-10:00AM
- Tutorial: STDF Fail Datalog Standard – Thursday, October 30, 8:30-10:00AM
