Structural Test Development Overview
Just a few years ago several manufacturers began making optimized structural testers that were more geared to processing Scan and BIST data and operations, as opposed to complex functional sequences. By doing this, the requirements on the ATE were significantly reduced and this in turn reduced the cost associated with the creation of the tester. The market that supports Scan and BIST techniques uses automatic test pattern generation (ATPG) and design-for-test (DFT) techniques to increase the quality metric and to reduce the time-to vectors. The goal here is more about "time-to-market" rather than "test cost."
DFT Case Studies
The Design Debug Application
Definition - The use of the structural test system by a Design, DFT, or Validation engineer; predominantly on a desktop which may be in a cubicle or office, or possibly in a lab environment.
Purpose - To use the instrument in the design environment for test chip and final device characterization, first silicon bring-up, and experiments. All of these tasks are to understand the device with respect to the design goals.
Key Driver - Capabilities: From the designer's point of view, the question asked is, "Do I have the capabilities and resources necessary to conduct the measurements required for characterization, bring-up, and experiments; or to assess my silicon against my specifications, goals, and the design library?"
Focus - To link the desktop structural "instrument" to design-side tools - simulators, ATPG engines, waveform viewers, and even tools such as static timing analysis and layout viewers.
New Directions - Investigations of using the tester to drive emulation configurations, or on conducting simulation acceleration using large FPGAs. The structural tester can be viewed as a reusable and configurable testbench or testbench driver. Another new focus in the first silicon and characterization space is the use of EDA tools and voltage manipulation techniques to auto-debug scan chains. The growth in this area is in the capabilities of the EDA tools which feed the structural testers and receive feedback data from them.
Inovys Solutions for Design Debug
