Verigy - Inovys Silicon Debug

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Inovys Silicon Debug

Rapidly detect, diagnose and visualize electrical failures on complex SOC devices shortening time to debug, ramp and volume production.

Accelerate the time for defect detection and diagnosis by efficient mapping of electrical failures to physical defects using logic bitmaps.
Uniquely find certain elusive defects while the device is on the tester.
Enable efficient collaboration between design and test through an integrated toolset.
Improve productivity and utilization of installed V93000 systems.
Leverage key learnings from best-in-class industry techniques and methods in a standard toolset and test program development

The Inovys Silicon Debug Solution is a suite of tools that provides a comprehensive solution that decreases the time previously needed for defect detection and diagnosis by efficiently mapping electrical failures to physical defects through logic bitmaps. The Silicon Debug solution uniquely finds certain previously elusive faults while complex SOC devices are still on the tester. The solution enables the ability to efficiently collaborate between design and test through an integrated toolset. It also successfully leverages multiple key learnings obtained from best-in-class industry techniques and methods and consolidates them in a standard toolset and test program development.

Solution Overview

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Inovys Silicon Debug

Features & Benefits

Key Specifications

The Inovys Silicon Debug Solution for the V93000 provides proprietary fault-targeted approaches to localizing failures in real time (while the part is still on the tester) to more efficiently debug new devices and accelerate time to volume production. Its key component, FaultInsyte, provides the most complete approach for systematic and parametric fault localization in the industry, on the industry's premier SOC tester, while reporting actionable information back in the language of the designer.

FaultInsyte provides high-speed automated localization and analysis of hard to find faults such as blocked chains and hold-time faults (Vddmin problems) in chains.

New, complex SOC designs can now be accelerated through the debug and production process by interrogating on-chip DFT structures with structural test methodologies running on more efficient test systems. The Silicon Debug solution combines the revolutionary Inovys FaultInsyte software with the Verigy V93000 SOC test system to display structural, hierarchical and physical views of DfT failures. It is the first tool that can link a chip's failure data with its design hierarchy and layout. These capabilities allow the analyst to interpret first silicon data in minutes.