Verigy - FaultInsyte Software

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FaultInsyte
Analysis Software for Silicon Debug and Failure Analysis

FaultInsyte is our award-winning, interactive test engineering debug and analysis suite, designed specifically for debug, characterization and failure analysis of complex SOC devices with advanced structural test. FaultInsyte works in conjunction with our Personal Ocelot and ZFP tester platforms.

New, complex SOC designs can now be accelerated through the debug and production process by interrogating on-chip DFT structures with structural test methodologies running on more efficient test systems. FlopPlot is a software analysis tool that displays different views of DFT failures and is the first tool that can link a chip's failure data with its design hierarchy and layout.

Interpret and analyze first silicon failure data in minutes
Link failure data to chip design hierarchy and layout
Track and review failures by individual or multiple devices
Identify gate-level faults by linking to diagnostic tools from Cadence, Magma Mentor Graphics, and Synopsys
Increase yield by systematically identifying failure distribution
View and analyze wafer level data
Perform high speed trace of the cone of logic driving the failures of difficult defects such as:

Blocked chain defects
Vdd min and Vdd max defects

View and analyze AC performance data to get a "shmoo at every flip-flop"
Faster analysis of structural test data generated by Inovys systems -- "Personal Ocelot" for desktop IC debug, characterization and validation and the "Ocelot ZFP" for high-volume manufacturing.

Product Overview

147KB

FaultInsyte

Features & Benefits

Key Specifications

Faster Problem Resolution for Complex Designs
FaultInsyte provides proprietary fault targeted approaches to localize the issue while the part is still in the socket to more efficiently debug new devices and accelerate time to volume production. FaultInsyte provides the most complete solution for systematic and parametric fault localization in the industry.

ATPG Output Flows Directly to Test System
All commercial ATPG tools generate STIL (IEEE1450 Standard Test Interface Language) files. Stylus™, the Inovys test system OS, loads and executes STIL files directly without additional translation steps. With this information, the test system can attach every failure to a flip-flop and pattern for fast analysis and then link to ATPG diagnostic tools to identify faults down to the gate-level.