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FaultInsyte
Analysis Software for Silicon Debug and Failure Analysis
FaultInsyte is our award-winning, interactive test engineering debug and analysis suite, designed specifically for debug, characterization and failure analysis of complex SOC devices with advanced structural test. FaultInsyte works in conjunction with our Personal Ocelot and ZFP tester platforms.
New, complex SOC designs can now be accelerated through the debug and production process by interrogating on-chip DFT structures with structural test methodologies running on more efficient test systems. FlopPlot is a software analysis tool that displays different views of DFT failures and is the first tool that can link a chip's failure data with its design hierarchy and layout.
- Interpret and analyze first silicon failure data in minutes
- Link failure data to chip design hierarchy and layout
- Track and review failures by individual or multiple devices
- Identify gate-level faults by linking to diagnostic tools from Cadence, Magma Mentor Graphics, and Synopsys
- Increase yield by systematically identifying failure distribution
- View and analyze wafer level data
- Perform high speed trace of the cone of logic driving the failures of difficult defects such as:
- Blocked chain defects
- Vdd min and Vdd max defects
- View and analyze AC performance data to get a "shmoo at every flip-flop"
- Faster analysis of structural test data generated by Inovys systems -- "Personal Ocelot" for desktop IC debug, characterization and validation and the "Ocelot ZFP" for high-volume manufacturing.
Product Overview  147KB
FaultInsyte
Import and View Structural Test Data
- Structural View: By scan-chain structure
- Hierarchal View: By design architecture
- Physical View: By physical layout (wafer or die level)
- Histogram View: Sort by speed
Link to Physical Layout Database
- Provides defect to layout overlay
- Trace functions (Fan in, fan out)
- Generate IP protected trace picture (i.e. Splat)
Track & Filter by Multiple Fail Variables
- Structural Test: Scan chains, bits in chain, scan patterns, pattern set, etc.
- Manufacturing: Program rev, lot ID, wafer ID, facility, XY coordinate, etc.
- Pattern Content: execs, bursts, specs, test IDs, etc.
Powerful GUI for Visual Variables
- Zoom to any level of detail within View
- Adjust color thresholds to filter failures by numerical intensity
- Intuitive displays show complete design data on any hierarchy or bit cell
Interfaces with Leading Tools, Including:
- Mentor Graphics FastScan™
- Synopsys TetraMAX™
- Cadence Encounter™
- Magma Talus™
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