Verigy - FlopPlot Software

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FlopPlot™

A suite of software analysis tools that display multiple views of device failures, FlotPlot uniquely links a chip's failure data with its design hierarchy and layout.

New, complex SOC designs can now be accelerated through the debug and production process by interrogating on-chip DFT structures with structural test methodologies running on more efficient test systems. FlopPlot is a software analysis tool that displays different views of DFT failures and is the first tool that can link a chip's failure data with its design hierarchy and layout.

Interpret and analyze first silicon failure data in minutes
Link failure data to chip design hierarchy and layout
Track and review failures by individual or multiple devices
Identify gate-level faults by linking to diagnostic tools from Mentor Graphics, Synopsys, and Cadence
Increase yield by systematically identifying failure distribution
Faster analysis of structural test data generated by the -- "Personal Ocelot"
for desktop IC debug, characterization and validation and the "Ocelot" and "Ocelot ZFP" for high-volume manufacturing.

Product Overview

240KB

FlopPlot™

Features & Benefits

Key Specifications

Faster Problem Resolution for Complex Designs
Large, complex SOC and ASIC designs can generate immense amounts of failure data, which is nearly impossible to interpret and analyze. FlopPlot was developed to handle this large volume of data and convert it into easy to understand information. FlopPlot contains a powerful software tool suite that enables DFT, Test, and FA professionals to quickly identify and resolve failures in very complex devices. In very large designs with millions of gates, failures are easily interpreted through image enhancement techniques.

ATPG Output Flows Directly to Test System
All commercial ATPG tools generate STIL (IEEE1450 Standard Test Interface Language) files. Stylus™, the Inovys test system OS, loads and executes STIL files directly without additional translation steps. With this information, the test system can attach every failure to a flip-flop and pattern for fast analysis and then link to ATPG diagnostic tools to identify faults down to the gate-level.