A suite of software analysis tools that display multiple views of device failures, FlotPlot uniquely links a chip's failure data with its design hierarchy and layout.

New, complex SOC designs can now be accelerated through the debug and production process by interrogating on-chip DFT structures with structural test methodologies running on more efficient test systems. FlopPlot is a software analysis tool that displays different views of DFT failures and is the first tool that can link a chip's failure data with its design hierarchy and layout.

• Interpret and analyze first silicon failure data in minutes
• Link failure data to chip design hierarchy and layout
• Track and review failures by individual or multiple devices
• Identify gate-level faults by linking to diagnostic tools from Mentor Graphics, Synopsys, and Cadence
• Increase yield by systematically identifying failure distribution
  Faster analysis of structural test data generated by the -- "Personal Ocelot"
  for desktop IC debug, characterization and validation and the "Ocelot" and "Ocelot ZFP" for high-volume manufacturing.

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