Inovys DfX Solutions has uniquely bridged the gap between the Electronic Design Automation (EDA) and test worlds. One of the keys to providing a seamless path between design and production, is the IEEE1450 Standard Test Interface Language (STIL) which is embedded in the core of our architecture. Inovys DfX Solutions has developed a comprehensive suite of tools which enable semiconductor companies to reduce design debug from weeks to hours, lower production test costs by a factor of 4, and supports real-time yield enhancements with unique failure analysis tools. Inovys has created the fastest path to profit for the semiconductor industry by creating unique tools for debug, diagnostics and yield learning.

Scan Chain Failure Mechanisms
ChainAnalyzer can isolate hundreds of blocked chain defects and now, for the first time, can also isolate Min/Max-Vdd or hold time defects as well.

DFT Based AC Analysis
SpeedScan is our revolutionary tool that provides "shmoo at every flip-flop" enabling up to millions of observation points per die for performance analysis. ScanImager works in conjunction with our FaultInsyte package of debug and diagnostic tools.

System Test Feedback
ScanImager is our IJTAG image comparison tool that allows the analyst to compare system test results to final test providing analysis and visualization tools for system test and for final test escapes. ScanImager works in conjunction with our FaultInsyte package of debug and diagnostic tools.