Our unique approach using automated fault localization while the part is still on the tester, provides very high speed localization of hard to manage faults such as blocked scan chains. Blocked chain faults have become the bain of DFT and failure analysis engineers at 90nm and below due to the increasing prevalence of these faults in the more advanced technology nodes.

Failing wafers produce hundreds of gigabits of fail information per wafer leading to intractable data handling problems and failure of traditional approaches. Our approach to blocked chain analysis reduces the data to a few kilobytes describing the location and net of the failure, in the language of the designer.

In addition the data can be exported. The FaultInsyte and YieldVision packages include export and import links to the EDA tools from Cadence, Magma, Mentor and Synopsys. This facilitates communication with the designer. The data can also be exported and imported to the fab's Yield Management System in the industry standard KLARF format.

What's broken? Where is it? How does it fail? Weather you need to communicate to design organization or to the fab you're ready.

Our unique approach using automated fault localization while the part is still on the tester, provides very high speed localization of hard to manage faults such as hold time faults in chains. These faults are also known as Vdd min problems since they are often voltage dependent. This can lead to poor yield at process corners and yield excursions due to narrow process windows. Hold time defects have been increasing, particularly for 65nm processes and below.

In addition to voltage dependencies, hold time faults often exhibit data dependencies. In some cases, both "0" and "1" data are affected. These can be thought of as a simple skipped bit problem. In other cases, the problem may be a dropped "0" with and aggressor "1" or a dropped "1" with an aggressor "0". These faults lead to a smearing of the data only for specific logic transitions.

Given the complexity of the problem and the need to bin the faults properly, it is necessary to create new patterns in real time while the part is in the socket. This allows separation from blocked chains, segregation by data dependency and an understanding of the voltage dependency. The data are output as a few kilobytes describing the location and net of the failure, in the language of the designer.

Often you will find that 99% of the design operates throughout the voltage specification. Fixing the exceptions can provide a stable process and stable yields.

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