SpeedScan queries the observation flip-flops, in user selectable steps, throughout the expected operating frequency, for all of the path path delay and transition delay patterns and logs the passing frequencies. Rather that a single failing frequency per die, you get the operating frequencies for hundreds-of-thousands or millions of observatiuon points per die. This provides the data for a "shmoo at every flip-flop".

The data can be displayed as histograms of maximum operating frequency by flip-flop and as die maps showing a pictorial view of the slower regions of the die. Full wafer analysis is possible allowing analysis of corners lots or of focus/exposure maps from a design-of-experiments approach to understand the electrical operating window for lithography. The data can be exported to EDA tools from Cadence, Magma, Mentor and Synopsys to allow fault simulation or comparisons to static timing analysis. The data can also be exported to Yield Management Systems to allow comparison to Process Window Characterization data from inspection tool vendors such as KLA-Tencor.

How fast are the parts? How big is the performance process window? Which circuit elements limit performance? Let SpeedScan help you exceed your limits.



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