With the Verigy V6000e, engineers now have a cost-effective, flexible, fully compatible, scalable test solution that offers the robust test capabilities of much larger solutions in a form factor suitable for an office or lab.
Like the V6000 WS and FT, the V6000e is supported by patent-pending Active Matrix technology, which delivers breakthrough cost of test (COT), as well as the scalability and flexibility required to perform both Flash and DRAM testing on the same system.

By providing a driver and comparator for each pin, and maintaining signal integrity and isolation, the V6000e test solution with Active Matrix improves yield and reduces cost per pin by 50 percent compared to a traditional tester.

With the simple installation of a new loadboard, the V6000e can test either DRAM or Flash memory, allowing engineers the flexibility to meet market conditions quickly and easily on one tester.

Because the V6000e has the same operating system software, hardware and interface of Verigy’s V6000 Series WS and FT test solutions, moving to the manufacturing floor is easy.

The V6000 platform’s scalability and versatility will allow manufacturers to extend the useful life of the tester, through a series of upgrades, well into the future.

Revolutionary Active Matrix

With the V6000 test solutions, Verigy introduces Active Matrix, the innovative patent-pending technology that enables increased throughput through increased parallelism, and increased yield through improving signal fidelity.

Four times the number of pins = four times the parallelism at half the cost per pin

• Pin electronics are moved to the interface layer, located in a cost-optimized pin electronics ASIC to achieve up to 18K pins per system
• Custom ASICs with drivers and comparators, produce four times the parallelism of traditional test solutions, at significantly lower costs (50 percent less per pin)
• Matches or exceeds the parallelism of other testers, without the signal degradation caused by sharing pins or the yield loss caused by shorted pins on a shared channel

75 percent reduction in distance between the pin electronics and probe card improves signal fidelity and yield

• Active Matrix ASIC enables close proximity to the probe card to provide optimal signal performance and parallel reads
• Reduced capacitive load-to-drive helps to eliminate excessive guard banding caused by long tester transmission lines that don’t match real-world device environments

Product Overview     56KB