The V6000 WS memory test system with new patent-pending Active Matrix technology delivers versatility, scalability and breakthrough cost-of-test (COT) that manufacturers need for both Flash and DRAM testing. The V6000 WS delivers the lowest COT in the industry through:

• Highest parallelism
• 300mm one touch-down DRAM, NOR and NAND test
• Scalability in AC performance - 140, 280, 560 Mbps - and parallelism (up to 18K I/O pins + 4K PPS (programmable power supply))
• Active Matrix improves yield with no compromise to signal integrity

The revolutionary Active Matrix both improves yield and reduces cost per pin by 50 percent compared to a traditional tester, by providing a driver and comparator for each pin, and maintaining signal integrity and isolation. It enables 300 mm one-touchdown probing on most devices.

With the simple installation of a new probecard, the V6000 WS can test either DRAM or Flash memory, allowing manufacturers to shift production volumes quickly and easily to meet market conditions and maximize profits.

The V6000 WS also uses low-cost, connectorless probe cards, and also has the ability to use different size probe cards (450mm or 560mm).

The V6000 WS interfaces to all major probers.

The V6000 utilizes the same operating system software, hardware and interface as the V6000e and V6000 FT, making test programs portable from engineering and characterization to wafer sort and final test.

The V6000 is water-cooled, requiring a smaller footprint than air-cooled systems.

The V6000 platform's scalability and versatility will allow manufacturers to extend the useful life of the tester through a series of upgrades, well into the future.

Revolutionary Active Matrix

With the V6000 test solutions, Verigy introduces Active Matrix, the innovative patent-pending technology that enables increased throughput through increased parallelism, and increased yield through significantly improved signal fidelity.

Four times the number of pins = four times the parallelism at half the cost per pin

• Pin electronics are moved to the interface layer, located in a cost-optimized pin electronics ASIC to achieve up to 18K pins per system
• Custom ASICs with drivers and comparators, produce four times the parallelism of traditional test solutions, at significantly lower costs (50 percent less per pin)
• Matches or exceeds the parallelism of other testers, without the signal degradation caused by sharing pins or the yield loss caused by shorted pins on a shared channel

75 percent reduction in distance between the pin electronics and probe card improves signal fidelity and yield

• Active Matrix ASIC enables close proximity to the probe card to provide optimal signal performance and parallel reads
• Reduced capacitive load-to-drive helps to eliminate excessive guard banding caused by long tester transmission lines that don’t match real-world device environments

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