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High-Speed I/O Test
Affordable, functional testing of high-speed SOCs up to 3.6 Gbps
The evolution of devices with increasingly complex semiconductors drives up the need for affordable nanometer SOC high-speed testing.
Verigy's high-speed testing solution provides the speed (up to 3.6 Gbps) and necessary accuracy (pin EPA < ± 30ps) at an unprecedented price (available for under $1.8 million*; additional high-speed pins can be added for as low as $2,000 per pin). Based on the Pin Scale 3600
Digital Card, each pin can be scaled through software configuration from 800 Mbps to 3.6 Gbps, allowing the test system to be configured to
match device requirements, pin-by-pin, for lowest cost. In addition to the scalability of memory depth and data rate, each pin offers both
single-ended and differential I/O test capabilities that make it possible to test a wide range of interfaces. The Pin Scale 3600 architecture includes two drivers, one to offer maximum compatibility with tests developed for the V93000 P-models, the other to support higher data rates up to 3.6 Gbps. Such flexibility provides bidirectional upstream/downstream compatibility and protects investments in equipment, people and
training.
*This complete PC chipset solution is comprised of the V93000 SOC Series, Pin Scale 3600 Digital Cards and associated software, services and
support. It is configured with more than 600 Pin Scale 3600 pins, with more than 250 pins operating at 1.8 or 3.2 Gbps.
Product Overview  704KB
High-Speed I/O Test
| Up to 3.6 Gbps I/O data rate |
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Supports characterization and design validation of current and emerging high-speed interfaces; provides greater margin to stress the device. |
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| Differential pin EPA of less than ± 30 ps |
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Better results and improved yield. |
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| Per-pin software configurable from 800 Mbps to 3.6 Gbps |
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Adapts to a broad range of device interfaces. Any pin, any speed, instantly. |
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| DUT board design based upon device requirements |
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DUT board design is not dependent on the ATE, thereby shortening time-to-market. |
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| 8 clock domains |
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Maximum flexibility to accommodate different speed fractions and device types. |
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| Scalable platform architecture |
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Protect existing investment in ATE with binary compatibility of test programs, ability to use existing DUT boards. |
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| 2,500 hours MTBF |
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Fewer components and proven water-cooling leads to higher reliability and higher utilization. |
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| Low entry price with cost-effective upgrades for the future |
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A complete 600+ pin solution, with over 250 high-speed pins (1.8 or 3.6 Gbps) is available for under $1.8M.
In addition, additional pins can be added for less than $2,000 per pin, making high-speed capability affordable.
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| Test Processor Per-Pin architecture |
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Localizes all test processing instead of using centralized resources, which results in minimal measurement overhead
and higher throughput.
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