Verigy - Yield Learning

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Yield Learning

Get to market on-time and maximize entitlement yield using the most comprehensive product based yield analysis solution in the industry.

The Yield Learning Solution provides on-tester capture and real-time statistical analysis of electrical failures on complex System-on-a-Chip (SOC) product die. It efficiently reduces large quantities of electrical failures from probed wafers or packaged parts into specific logical faults. The powerful suite of software analysis and visualization tools enable fast localization of the root cause physical defects, such as: stuck-at defects; timingfaults in scan chains and clock trees. The result is significantly faster time to problem diagnosis. The Yield Learning Solution:

Reduces time and number of wafers to achieve yield entitlement.
Enables achievement of maximum entitlement yield by eliminating process design interaction yield loss mechanisms
Increases responsiveness to yield excursions by reducing time to defect detection and diagnosis through a short loop, automated fault localization flow.
Significantly reduces data log volume by more than 1000x

The Yield Learning Solution consists of three elements:

On-tester Triage: With Triage software, large quantities of electrical failure data are efficiently collected on-tester at the wafer sort stage. Using proprietary algorithms, this data is reduced into a more manageable form showing logical faults.

Features and Benefits

YieldVision Analysis and Visualization Tools: The YieldVision analysis and visualization tools show the information in wafer maps, die maps and net maps. The data collected can be stacked and analyzed by die, by wafer, by complete wafer lots, or even across multiple lots by identifying faults with statistical significance.

Features and Benefits

Right Test Architecture: The V93000 SOC test system is engineered with the right test architecture, scalable to meet current and future complex SOC/SIP test challenges, and features the industries first on-the-tester fault localization tool.

Features and Benefits

Solution Overview

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Solution Summary Matrix

Key Specifications

Components / Options

Requirements

Solution

Volume yield ananalysis tools		Multi-wafer or multi-lot analysis tools including trending and visualization tools.

Improvement to tester- centric pin and cycle count format		On-tester conversion to pattern, chain and bit – In the language of the designer – In a design hierarchy context – With accurate x, y die coordinates

Layout extraction		Lightweight net trace from failing flip-flop providing cell and routing level visualization of failures

High-speed, on-tester solution for determining chain faults		On-the-tester adaptive pattern creation for chain failure localization to chain and bit – For blocked chains – For hold-time (Vdd min/max) faults

Adaptive sampling for statistically valid data collection		Automated control of sample rates with smart triggers allow user defined data collection for efficient collection of the data that you need.

Protection for design IP		IP Protected Splats – Client-server type interface to allow communication between the fabless company and the foundry that provides enough information to solve the problem without compromising IP

Link to EDA tools		Import/export solution to EDA tools from Cadence, Mentor Graphics and Synopsys

Ease of use		Award-winning graphical user interface (GUI) that allows any design for test (DFT), failure analysis (FA) or design engineer to say, "I can use it myself!"

Separates visible and non-visible defects		Performs KLARF import and overlay to electrical faults. Performs KLARF export to DMS/YMS tools.

Accuracy, stability, repeatability and reliability, flexibility and scalability		Proven V93000 architecture delivers