Yield Learning

Get to market on-time and maximize entitlement yield using the most comprehensive product based yield analysis solution in the industry.

The Yield Learning Solution provides on-tester capture and real-time statistical analysis of electrical failures on complex System-on-a-Chip (SOC) product die. It efficiently reduces large quantities of electrical failures from probed wafers or packaged parts into specific logical faults. The powerful suite of software analysis and visualization tools enable fast localization of the root cause physical defects, such as: stuck-at defects; timingfaults in scan chains and clock trees. The result is significantly faster time to problem diagnosis. The Yield Learning Solution:
  • Reduces time and number of wafers to achieve yield entitlement.
  • Enables achievement of maximum entitlement yield by eliminating process design interaction yield loss mechanisms
  • Increases responsiveness to yield excursions by reducing time to defect detection and diagnosis through a short loop, automated fault localization flow.
  • Significantly reduces data log volume by more than 1000x

The Yield Learning Solution consists of three elements:

On-tester Triage: With Triage software, large quantities of electrical failure data are efficiently collected on-tester at the wafer sort stage. Using proprietary algorithms, this data is reduced into a more manageable form showing logical faults.

Features and Benefits


YieldVision Analysis and Visualization Tools: The YieldVision analysis and visualization tools show the information in wafer maps, die maps and net maps. The data collected can be stacked and analyzed by die, by wafer, by complete wafer lots, or even across multiple lots by identifying faults with statistical significance.

Features and Benefits


Right Test Architecture: The V93000 SOC test system is engineered with the right test architecture, scalable to meet current and future complex SOC/SIP test challenges, and features the industries first on-the-tester fault localization tool.

Features and Benefits

Solution Overview  168 KB



Yield Learning Landing Page Image


Import and View Structural test data
  • Structural View: by Scan Chain Structure
  • Hierarchal View: by Design Architecture
  • Physical View: by Physical Layout (wafer or die level)
  • Histogram: Sort by Speed
Link to physical layout database
  • LEF/DEF interface
  • Trace functions (Fan in, fan out)
  • Generate IP protected trace picture (i.e. Splat)
Track and Filter by Multiple Fail Variables
  • Structural Test: Scan chains, bits in chain, scan patterns, pattern set, etc.
  • Manufacturing: program rev, lot ID, wafer ID, facility, XY coordinate, etc.
  • Pattern content: execs, bursts, specs, test IDs, etc.
Powerful GUI for Visual Variables
  • Zoom to any level of detail within View
  • Adjust color thresholds to filter failures by numerical intensity
  • Intuitive displays show complete design data on any hierarchy or bit cell
Direct links with Leading ATPG Tools, including:
  • Cadence Encounter Test
  • Mentor Graphics FastScan
  • Synopsis TetraMAX
Linux Based
  • Works in conjunction with any Pin Scale V93000
  • Available on SmartTest 6.5.2
Interfaces to
  • KLARF based inspection tools
  • DDMS/YMS