Analysis and visualization tools show information in wafer maps, die maps and net maps.
The Yield Learning Solution provides on-tester capture and real-time statistical analysis of electrical failures on complex System-on-a-Chip (SOC) product die. It efficiently reduces large quantities of electrical failures YieldVision provides a layout centric analysis and visualization platform that displays faults and groups of faults in three important views.
Structural View: Faults are displayed showing the faults in a simple row/column format where each row represents a scan chain and each column represents the bit position in that chain. This view provides the analyst with a logic bitmap view of faults in SOC devices, enabling the type of analysis traditionally limited to memory devices.
Hierarchical View: Faults are also displayed showing logic blocks and the design hierarchy. This enables the analyst to focus on specific elements of the design for debug, characterization or yield analysis, enabling parallel efforts on multiple issues without interference.
Physical View: Finally, the faults are displayed showing the physical location of the defect on the die. The physical view includes our unique “splat” level view showing specific net trace paths from the failing observation point. This capability enables fast localization of the root cause physical defects, such as: stuck-at defects; timing faults in scan chains; and clock trees. The result is significantly faster time to problem diagnosis.
1.12 MB