Published 28-May-2003

Abstract
The emerging IEEE standard, Core Test Language (CTL-P1450.6), is intended as a standard test methodology for embedded cores on a System on Chip (SOC). CTL demonstrates an efficient way to improve the reciprocal awareness between design and test. The Automatic Test Pattern Generators (ATPG), provide early automated test equipment (ATE) architecture and performance description information from design to generate vectors directly portable to the tester. In the reverse direction, the tester gains awareness of the test activation mechanism of the device under test (DUT) by reading the CTL-compliant data.

The adoption of P1451.6 promises significant improvement in cost of test and time to volume in manufacturing, when used in conjunction with automated test equipment (ATE) that can fully exploit its capabilities.

This paper explores the manufacturing test benefits of the proposed standard, the ATE capabilities needed to take full advantage of the new standard, and the joint efforts currently underway to create a highly automated test development environment that will support CTL.