Abstract
Automated test equipment (ATE) is used extensively in production test and device characterization of integrated circuits (ICs). With future devices forecasted to contain hundreds of I/O cells operating at speeds from 5Gb/s to 10Gb/s, the challenge to test those devices with an ATE system is becoming more complex. The speed bottleneck is moving from the pin electronics of the ATE to the DUT Loadboard that connects the ATE to the device under test (DUT). The layout of the DUT Loadboard will require thinner and longer signal traces which will have an unacceptable loss for the required data rates. This challenge will require the use of compensation techniques to address the increased loss of the signal traces. This article presents one strategy to address this challenge by integrating passive equalization in the DUT Loadboard signal trace. This article is a revised and extended version with new results of the article “Passive Equalization of Test Fixtures for High-Speed Digital Measurements with Automated Test Equipment” that was presented at the 2006 IEEE International Design and Test Workshop.